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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features up to 600 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of pro- gramming and compiler-friendly support advanced debug, trace, an d performance monitoring wide range of operating voltages (see operating conditions on page 20 ) qualified for automotive applications (see automotive prod- ucts on page 62 ) programmable on-chip voltage regulator 160-ball csp_bga, 169-ball pbga, and 176-lead lqfp packages memory up to 148k bytes of on-chip memory (see table 1 on page 3 ) memory management unit providing memory protection external memory controller with glueless support for sdram, sram, flash, and rom flexible memory booting options from spi and external memory peripherals parallel peripheral interface ppi, supporting itu-r 656 video data formats 2 dual-channel, full duplex synchronous serial ports, sup- porting eight stereo i 2 s channels 2 memory-to-memory dmas 8 peripheral dmas spi-compatible port three 32-bit timer/counters with pwm support real-time clock and watchdog timer 32-bit core timer up to 16 general-purpose i/o pins (gpio) uart with support for irda event handler debug/jtag interface on-chip pll capable of frequency multiplication figure 1. function al block diagram uart sport0 - 1 watchdog timer rtc spi timer0 - 2 ppi gpio port f external port flash, sdram control boot rom jtag test and emulation voltage regulator dma controller l1 instruction memory l1 data memory d ma a c ce ss bu s dma core bus p er i p he r al a cc e ss b us dma external bus external access bus 16 interrupt controller b
rev. i | page 2 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 table of contents features ................................................................. 1 memory ................................................................ 1 peripherals ............................................................. 1 general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 processor peripherals ............................................. 3 blackfin processor core .......................................... 4 memory architecture ............................................ 4 dma controllers .................................................. 8 real-time clock ................................................... 8 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) ............................................ 9 serial peripheral interface (spi) port ....................... 10 uart port ........................................................ 10 general-purpose i/o port f ................................... 10 parallel peripheral interface ................................... 11 dynamic power management ................................ 11 voltage regulation .............................................. 13 clock signals ..................................................... 13 booting modes ................................................... 14 instruction set description ................................... 15 development tools .............................................. 15 additional information ........................................ 16 related signal chains ........................................... 16 pin descriptions .................................................... 17 specifications ........................................................ 20 operating conditions ........................................... 20 electrical characteristics ....................................... 22 absolute maximum ratings ................................... 25 esd sensitivity ................................................... 25 package information ............................................ 26 timing specifications ........................................... 27 output drive currents ......................................... 43 test conditions .................................................. 45 thermal characteristics ........................................ 49 160-ball csp_bga ball assignment .. ......................... 50 169-ball pbga ball assignment ... .............................. 53 176-lead lqfp pinout ... ......................................... 56 outline dimensions ................................................ 58 surface-mount design .......................................... 61 automotive products .............................................. 62 ordering guide ..................................................... 63 revision history 8/13 rev. h to rev. i updated development tools .................................... 15 corrected conditions value of the v il specification in operating conditions ............................................. 20 added notes to table 30 in serial portsenable and three-state .......................... 36 added timer clock timing ...................................... 41 revised timer cycle timing ..................................... 41 updated ordering guide ......................................... 63
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 3 of 64 | august 2013 general description the adsp-bf531/adsp-bf532/ad sp-bf533 processors are members of the blackfin ? family of products, incorporating the analog devices, inc./intel micr o signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthogonal risc- like microprocessor instruction se t, and single instruction, mul- tiple data (simd) multimedia capabilities into a single instruction set architecture. the adsp-bf531/adsp-bf532/ad sp-bf533 processors are completely code and pi n-compatible, differing only with respect to their performance and on-chip memory. specific perfor- mance and memory configurations are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power managementthe ability to vary both the volt- age and frequency of operation to significantly lower overall power consumption. varying the voltage and frequency can result in a substantial reduction in power consumption, com- pared with just vary ing the frequency of operation. this translates into longer battery life for portable appliances. system integration the adsp-bf531/adsp-bf532/a dsp-bf533 processors are highly integrated syst em-on-a-chip solutions for the next gener- ation of digital communication and consumer multimedia applications. by combining industry-standard interfaces with a high performance signal proce ssing core, users can develop cost-effective solutions quickly without the need for costly external components. the system peripherals include a uart port, an spi port, two serial po rts (sports), four general-pur- pose timers (three with pwm capability), a real-time clock, a watchdog timer, and a para llel peripheral interface. processor peripherals the adsp-bf531/adsp-bf532/a dsp-bf533 processors con- tain a rich set of peripherals co nnected to the core via several high bandwidth buses, providing flexibility in system configura- tion as well as excellent overall system performance (see the functional block diagram in figure 1 on page 1 ). the general- purpose peripherals include func tions such as uart, timers with pwm (pulse-width modulation) and pulse measurement capability, general-purpose i/o pins, a real-time clock, and a watchdog timer. this set of func tions satisfies a wide variety of typical system support needs an d is augmented by the system expansion capabilities of the part . in addition to these general- purpose peripherals, the processo rs contain high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the proces- sor and system to many application scenarios. all of the peripherals, except fo r general-purpose i/o, real-time clock, and timers, are supported by a flexible dma structure. there is also a separate memory dma channel dedicated to data transfers between the proc essors various memory spaces, including external sdram and asynchronous memory. multi- ple on-chip buses running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activ- ity on all of the on-chip and external peripherals. the processors include an on-chi p voltage regulator in support of the processors dynamic power management capability. the voltage regulator provides a rang e of core voltage levels from v ddext . the voltage regulator can be bypassed at the users discretion. table 1. processor comparison features adsp-bf531 adsp-bf532 adsp-bf533 sports 2 2 2 uart 1 1 1 spi 1 1 1 gp timers 3 3 3 watchdog timers 1 1 1 rtc 1 1 1 parallel peripheral interface 1 1 1 gpios 16 16 16 memory configuration l1 instruction sram/cache 16k bytes 16k bytes 16k bytes l1 instruction sram 16k bytes 32k bytes 64k bytes l1 data sram/cache 16k bytes 32k bytes 32k bytes l1 data sram 32k bytes l1 scratchpad 4k bytes 4k bytes 4k bytes l3 boot rom 1k bytes 1k bytes 1k bytes maximum speed grade 400 mhz 400 mhz 600 mhz package options: csp_bga plastic bga lqfp 160-ball 169-ball 176-lead 160-ball 169-ball 176-lead 160-ball 169-ball 176-lead
rev. i | page 4 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 blackfin processor core as shown in figure 2 on page 5 , the blackfin processor core contains two 16-bit mu ltipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-bit, 16- bit, or 32-bit data from the register file. the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and population count, modulo 2 32 multiply, divide primitives, satu- ration and rounding, and sign/exponent detection. the set of video instructions includes byte alignment and packing opera- tions, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compare/select and vector search instructions. for certain instructions, two 16- bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). quad 16-bit operations are possible using the second alu. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf531/adsp-bf532/a dsp-bf533 processors view memory as a single unified 4g by te address space, using 32-bit addresses. all resources, includ ing internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. the memory portions of this address space are arranged in a hi erarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or sram, and larger, lower cost and performance off-chip memory systems. see figure 3 , figure 4 , and figure 5 on page 6 . the l1 memory system is th e primary highest performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessi ng up to 132m bytes of physical memory. the memory dma controller prov ides high bandwidth data- movement capability. it can perf orm block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the processors have three blocks of on-chip memory that pro- vide high bandwidth access to the core. the first block is the l1 instruction memory, consisting of up to 80k bytes sram, of which 16k bytes can be configured as a four way set-associative cache. this memory is accessed at full processor speed.
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 5 of 64 | august 2013 the second on-chip memory block is the l1 data memory, con- sisting of one or two banks of up to 32k bytes. the memory banks are configurable, offering both cache and sram func- tionality. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram, which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the external bus interface unit (ebiu). this 16-bit interface prov ides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, eprom, rom, sram, and memory mapped i/o devices. the pc133-compliant sdram cont roller can be programmed to interface to up to 128m by tes of sdram. the sdram con- troller allows one row to be open for each internal sdram bank, for up to four internal sdram banks, improving overall system performance. the asynchronous memory cont roller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguo us if each is fully populated with 1m byte of memory. i/o memory space blackfin processors do not defi ne a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one containing the contro l mmrs for all core functions, and the other containing the regi sters needed for setup and con- trol of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the adsp-bf531/adsp-bf532/a dsp-bf533 processors con- tain a small boot kernel, which configures the appropriate peripheral for booting. if the pr ocessors are configured to boot from boot rom memory space, the processor starts executing from the on-chip boot rom. for more information, see boot- ing modes on page 14 . figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
rev. i | page 6 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 event handling the event controller on the proce ssors handle all asynchronous and synchronous events to th e processor. the adsp-bf531/ adsp-bf532/adsp-bf533 processo rs provide event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. pri- oritization ensures that servicing of a higher priority event takes precedence over servicing of a lo wer priority event. the control- ler provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow (i.e., the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. figure 3. adsp-bf531 inte rnal/external memory map figure 4. adsp-bf532 inte rnal/external memory map core mmr registers (2m byte) reserved scratchpad sram (4k byte) system mmr registers (2m byte) reserved reserved reserved data bank a sram/cache (16k byte) async memory bank 3 (1m byte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte to 128m byte) instruction sram/cache (16k byte) in t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa0 8000 0xff90 8000 0xff90 4000 0xff80 80 00 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved reserved 0xffa1 0000 instruction sram (16k byte) reserved reserved 0xffa0 c000 reserved core mmr registers (2m byte) reserved scratchpad sram (4k byte) system mmr registers (2m byte) reserved reserved data bank b sram/cache (16k byte) reserved data bank a sram/cache (16k byte) asyncmemorybank3(1mbyte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte to 128m byte) instruction sram/cache (16k byte) in t e r n a l m e m o r y m a p ex te r n a l m e m o ry m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa0 8000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved reserved 0xffa1 0000 instruction sram (32k byte) reserved figure 5. adsp-bf533 internal/external memory map reserved core mmr registers (2m byte) reserved scratchpad sram (4k byte) instruction sram (64k byte) system mmr registers (2m byte) reserved reserved data bank b sram/cache (16k byte) data bank b sram (16k byte) data bank a sram/cache (16k byte) async memory bank 3 (1m byte) async memory bank 2 (1m byte) async memory bank 1 (1m byte) async memory bank 0 (1m byte) sdram memory (16m byte to 128m byte) instruction sram/cache (16k byte) in t er n a l m em o r y m ap e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved data bank a sram (16k byte) 0xff90 0000 0xff80 0000 reserved
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 7 of 64 | august 2013 each event type has an associated register to hold the return address and an associated return-from-event instruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the adsp-bf531/adsp-bf532/adsp -bf533 processors event controller consists of two stages , the core event controller (cec) and the system interrupt contro ller (sic). the core event con- troller works with the system in terrupt controller to prioritize and control all system events. co nceptually, interrupts from the peripherals enter into the sic, an d are then routed directly into the general-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest priority inter- rupts (ivg15C14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processors provid e a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (sic_iarx). table 3 describes the inputs into the sic and the default mappings into the cec. event control the processors provide a very flexible mechanism to control the processing of events. in the ce c, three registers are used to coordinate and control events. ea ch register is 32 bits wide: ? cec interrupt latch register (ilat) C the ilat register indicates when events have been latched. the appropriate bit is set when the processo r has latched the event and cleared when the even t has been accepted into the system. this register is updated automatically by the controller, but it can also be written to clear (cancel) latched events. this register can be read while in supervisor mode and can only be written while in supervisor mode when the correspond- ing imask bit is cleared. ? cec interrupt mask register (imask) C the imask regis- ter controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when asserted. a cleared bit in the imask register masks the event, preventing the processor fr om servicing the event even though the event may be latched in the ilat register. this register can be read or written while in supervisor mode. note that general-purpose interrupts can be globally enabled and disabled with the sti and cli instructions, respectively. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1reset rst 2 nonmaskable interrupt nmi 3exceptionevx 4reserved 5 hardware error ivhw 6 core timer ivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15 table 3. system interrupt controller (sic) peripheral interrupt event default mapping pll wakeup ivg7 dma error ivg7 ppi error ivg7 sport 0 error ivg7 sport 1 error ivg7 spi error ivg7 uart error ivg7 real-time clock ivg8 dma channel 0 (ppi) ivg8 dma channel 1 (sport 0 receive) ivg9 dma channel 2 (sport 0 transmit) ivg9 dma channel 3 (sport 1 receive) ivg9 dma channel 4 (sport 1 transmit) ivg9 dma channel 5 (spi) ivg10 dma channel 6 (uart receive) ivg10 dma channel 7 (uart transmit) ivg10 timer 0 ivg11 timer 1 ivg11 timer 2 ivg11 port f gpio interrupt a ivg12 port f gpio interrupt b ivg12 memory dma stream 0 ivg13 memory dma stream 1 ivg13 software watchdog timer ivg13
rev. i | page 8 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 ? cec interrupt pending regi ster (ipend) C the ipend register keeps track of all nested events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but can be re ad while in supervisor mode. the sic allows further control of event processing by providing three 32-bit interrupt control and status registers. each register contains a bit corresponding to each of the peripheral interrupt events shown in table 3 . ? sic interrupt mask register (sic_imask) C this register controls the masking and unma sking of each peripheral interrupt event. when a bit is set in this register, that peripheral event is unmasked and is processed by the sys- tem when asserted. a cleared bi t in this register masks the peripheral event, preventing the processor from servicing the event. ? sic interrupt status regist er (sic_isr) C as multiple peripherals can be ma pped to a single event, this register allows the software to dete rmine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable register (sic_iwr) C by enabling the correspo nding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. see dynamic power management on page 11 . because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interr upt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recogn izes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general-purpose interrupt to the ipend output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. dma controllers the adsp-bf531/adsp-bf532/ad sp-bf533 processors have multiple, independent dma chan nels that support automated data transfers with minimal overhead for the processor core. dma transfers can occur between the processors internal memories and any of its dma-ca pable peripherals. addition- ally, dma transfers can be acco mplished between any of the dma-capable peripherals and exte rnal devices connected to the external memory interfaces, including the sdram controller and the asynchronous memory controller. dma-capable peripherals include the sports, spi port, uart, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the dma controller supports both 1-dimensional (1-d) and 2- dimensional (2-d) dma transfers. dma transfer initialization can be implemented from register s or from sets of parameters called descriptor blocks. the 2-d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video a pplications where data can be de-interleaved on the fly. examples of dma types suppo rted by the dma controller include: ? a single, linear buffer that stops upon completion ? a circular, autorefreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two pairs of memory dma cha nnels provided for transfers between the various memories of the processor system. this enables transfers of blocks of data between any of the memo- riesincluding external sdram, rom, sram, and flash memorywith minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. real-time clock the processor real-time clock (rtc) provides a robust set of digital watch features, includin g current time, stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the adsp-bf531/adsp-bf532/ad sp-bf533 processors. the rtc peripheral has dedicated powe r supply pins so that it can remain powered up and clocked ev en when the rest of the pro- cessor is in a low power stat e. the rtc provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counte r function of the timer consists of four counters: a 60 second co unter, a 60 minute counter, a 24 hour counter, and a 32,768 day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. the two alarms are time of day and a day and time of that day.
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 9 of 64 | august 2013 the stopwatch function counts down from a programmed value, with one second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like other peripherals, the rtc can wake up the processor from sleep mode upon generation of any rtc wakeup event. additionally, an rtc wakeup ev ent can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state. connect rtc pins rtxi and rtxo with external components as shown in figure 6 . watchdog timer the adsp-bf531/adsp-bf532/adsp-bf533 processors include a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system availability by forcing the proc essor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software mu st reload the counter before it counts to zero from the progra mmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the system clock (sclk), at a maximum frequency of f sclk . timers there are four general-purpose programmable timer units in the adsp-bf531/adsp-bf532/a dsp-bf533 processors. three timers have an external pin that can be configured either as a pulse-width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events . these timers can be synchro- nized to an external clock inpu t to the pf1 pin (taclk), an external clock input to the ppi_clk pin (tmrclk), or to the internal sclk. the timer units can be used in conjunction with the uart to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel. the timers can generate interrupt s to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. in addition to the three genera l-purpose programmable timers, a fourth timer is also provided. this extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operatin g system periodic interrupts. serial ports (sports) the adsp-bf531/adsp-bf532/adsp-bf533 processors incorporate two dual-channel synchronous serial ports (sport0 and sport1) for serial and multiprocessor commu- nications. the sports suppo rt the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pins, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each tran smit and receive port can either use an external serial clock or gene rate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 bits to 32 bits in length, transferred most-signifi- cant-bit first or least-significant-bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. figure 6. external components for rtc rtxo c1 c2 x1 suggested components: x1 = ecliptek ec38j (through-hole package) or epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m : note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
rev. i | page 10 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 ? interrupts C each transmit a nd receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1,024-channel window and is compatible with the h.100, h.110, mvip-90, and hmvip standards. an additional 250 mv of sp ort input hysteresis can be enabled by setting bit 15 of the pll_ctl register. when this bit is set, all sport input pins have the increased hysteresis. serial peripheral interface (spi) port the adsp-bf531/adsp-bf532/ad sp-bf533 processors have an spi-compatible port that en ables the processor to communi- cate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input-slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the proces- sor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi devices. the spi select pins are recon- figured general-purpose i/o pins. using these pins, the spi port provides a full-duplex, synchronous serial interface which sup- ports both master/slave modes and multimaster environments. the baud rate and clock phase/po larities for the spi port are programmable, and it has an integrated dma controller, con- figurable to support transmit or receive data streams. the spi dma controller can only service un idirectional accesses at any given time. the spi port clock rate is calculated as: where the 16-bit spi_baud regist er contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart port the adsp-bf531/adsp-bf532/ad sp-bf533 processors pro- vide a full-duplex universal asynchronous receiver/transmitter (uart) port, which is fully compatible with pc-standard uarts. the uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-sup- ported, asynchronous transfers of serial data. the uart port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd pa rity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the baud rate, serial data format , error code generation and sta- tus, and interrupts for the uart port are programmable. the uart programmable features include: ? supporting bit rates ranging from (f sclk /1,048,576) bits per second to (f sclk /16) bits per second. ? supporting data formats from seven bits to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uart_divisor comes from the uart_dlh register (most significant 8 bits ) and uart_dll register (least significant 8 bits). in conjunction with the general-purpose timer functions, autobaud detection is supported. the capabilities of the uart ar e further extended with support for the infrared data association (irda ? ) serial infrared physi- cal layer link specification (sir) protocol. general-purpose i/o port f the adsp-bf531/adsp-bf532/a dsp-bf533 processors have 16 bidirectional, general-purpose i/o pins on port f (pf15C0). each general-purpose i/o pin can be individually controlled by manipulation of the gpio co ntrol, status and interrupt registers: ? gpio direction control register C specifies the direction of each individual pfx pin as input or output. ?gpio control and status regi sters C the processor employs a write one to modify mechanism that allows any combi- nation of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. four control registers ar e provided. one register is written in order to set gpio pin values, one register is writ- ten in order to clear gpio pin values, one register is written in order to toggle gpio pin valu es, and one register is writ- ten in order to specify gpio pin values. reading the gpio status register allo ws software to interrogate the sense of the gpio pin. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each indivi dual pfx pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual gpio pin values, one gpio in terrupt mask register sets bits to enable interrupt function, and the other gpio inter- rupt mask register clears bits to disable interrupt function. spi clock rate f sclk 2 spi_baud ? ----------------------------------- - = uart clock rate f sclk 16 uart_divisor ? ----------------------------------------------- =
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 11 of 64 | august 2013 pfx pins defined as inputs can be configured to generate hardware interrupts, while output pfx pins can be trig- gered by software interrupts. ? gpio interrupt sensitivity re gisters C the two gpio inter- rupt sensitivity registers sp ecify whether individual pfx pins are level- or edge-sensiti ve and specifyif edge-sensi- tivewhether just the rising edge or both the rising and falling edges of the signal ar e significant. one register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. parallel peripheral interface the processors provide a parallel peripheral interface (ppi) that can connect directly to parallel adcs and dacs, video encod- ers and decoders, and other gene ral-purpose peripherals. the ppi consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general- purpose mode, the ppi provides half-duplex, bi-directi onal data transfer with up to 16 bits of data. up to three frame synchr onization signals are also pro- vided. in itu-r 656 mode, the ppi provides half-duplex bi- directional transfer of 8- or 10-bit video data. additionally, on- chip decode of embedded start- of-line (sol) and start-of-field (sof) preamble pack ets is supported. general-purpose mode descriptions the general-purpose modes of th e ppi are intended to suit a wide variety of data capture and transmission applications. three distinct sub modes are supported: ? input mode C frame syncs and data are inputs into the ppi. ? frame capture mode C frame syncs are outputs from the ppi, but data are inputs. ? output mode C frame syncs an d data are outputs from the ppi. input mode input mode is intended for adc applications, as well as video communication with hardware sign aling. in its simplest form, ppi_fs1 is an external frame sync input that controls when to read data. the ppi_delay mmr allows for a delay (in ppi_- clk cycles) between reception of this frame sync and the initiation of data reads. the nu mber of input data samples is user programmable and defined by the contents of the ppi_count register. the ppi supports 8-bit and 10-bit through 16-bit data, programmable in the ppi_control register. frame capture mode frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). the processors control when to read from the video source(s). ppi_fs1 is an hsync output and ppi_fs2 is a vsync output. output mode output mode is used for transmitting video or other data with up to three output frame syncs. typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. itu-r 656 mode descriptions the itu-r 656 modes of the ppi are intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct sub modes are supported: ?active video only mode ? vertical blanking only mode ? entire field mode active video only mode active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. the ppi does not read in any da ta between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. afte r synchronizing to the start of field 1, the ppi ignores incoming samples until it sees an sav code. the user specifies the number of active video lines per frame (in ppi_count register). vertical blanking interval mode in this mode, the ppi only transf ers vertical blanking interval (vbi) data. entire field mode in this mode, the entire incoming bit stream is read in through the ppi. this includes active vide o, control preamble sequences, and ancillary data that can be embedded in horizontal and verti- cal blanking intervals. data transfer starts immediately after synchronization to field 1. data is transferred to or from the synchronous channels through eight dma engines that work autonomously from the processor core. dynamic power management the adsp-bf531/adsp-bf532/a dsp-bf533 processors pro- vides four operating modes, each with a different performance/ power profile. in addition, dynamic power management pro- vides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. control of clocking to each of the processor peripherals also reduces power consumption. see table 4 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed.
rev. i | page 12 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 active operating modemoderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropri ately configured l1 memories. in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before it can transition to the full-on or sleep modes. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc activity will wake up the processor. when in the sleep mo de, assertion of wakeup causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the proces- sor will transition to the full-on mode. if bypass is enabled, the processor will transition to the active mode. when in the sleep mode, system dma access to l1 memory is not supported. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the proces- sor to transition to the ac tive mode. assertion of reset while in deep sleep mode causes the pr ocessor to transition to the full- on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and to all the synchronous peripherals (sclk). the internal voltage regulator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl regi ster. in addition to disabling the clocks, this sets the internal power supply voltage (v ddint ) to 0 v to provide the lowest static power dissipation . any critical information stored internally (memory contents , register con- tents, etc.) must be written to a nonvolatile storage device prior to removing power if the proce ssor state is to be preserved. since v ddext is still supplied in this mode, all of the external pins three-state, unless otherwis e specified. this allows other devices that may be connected to the processor to still have power applied without drawing un wanted current. the internal supply regulator can be woken up either by a real-time clock wakeup or by asserting the reset pin. power savings as shown in table 5 , the processors support three different power domains. the use of multiple power domains maximizes flexibility, while maintaining compliance with industry stan- dards and conventions. by isolating the internal logic of the processor into its own power domain, separate from the rtc and other i/o, the processor can take advantage of dynamic power management without affecting the rtc or other i/o devices. there are no sequencing requirements for the various power domains. the power dissipated by a processo r is largely a function of the clock frequency of the processor and the square of the operating voltage. for example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, thes e power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the savings in power dissipation can be modeled using the power savings factor and % p ower savings calculations. the power savings factor is calculated as: where the variables in the equation are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage table 4. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) internal power (v ddint ) full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off table 5. power domains power domain v dd range all internal logic, except rtc v ddint rtc internal logic and crystal i/o v ddrtc all other i/o v ddext power savings factor f cclkred f cclknom --------------------- v ddintred v ddintnom -------------------------- ?? ?? 2 ? t red t nom ---------- - ? ? ? ? ? =
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 13 of 64 | august 2013 t nom is the duration running at f cclknom t red is the duration running at f cclkred the percent power savings is calculated as: voltage regulation the blackfin processo r provides an on-chip voltage regulator that can generate appropriate v ddint voltage levels from the v ddext supply. see operating conditions on page 20 for regula- tor tolerances and acceptable v ddext ranges for specific models. figure 7 shows the typical external components required to complete the power management system. the regulator con- trols the internal logic voltage le vels and is programmable with the voltage regulator control regi ster (vr_ctl) in increments of 50 mv. to reduce standby po wer consumption, the internal voltage regulator can be progra mmed to remove power to the processor core while keeping i/o power (v ddext ) supplied. while in the hibernate state, i/o power is still being applied, eliminating the need for external buffers. the voltage regulator can be activated from this power-down state either through an rtc wakeup or by asserting reset , both of which initiate a boot sequence. the regulator can also be disabled and bypassed at the users discretion. voltage regulator layout guidelines regulator external component pl acement, board routing, and bypass capacitors all have a significant effect on noise injected into the other analog circuits on-chip. the vrout1C0 traces and voltage regulator external components should be consid- ered as noise sources when doing board layout and should not be routed or placed near sensitiv e circuits or co mponents on the board. all internal and i/o power supplies should be well bypassed with bypass capacitors pl aced as close to the proces- sors as possible. for further details on the on-chi p voltage regulator and related board design guidelines, see the switching regulator design considerations for adsp-bf533 blackfin processors (ee-228) applications note on the analog devices web site ( www.ana- log.com )use site search on ee-228. clock signals the adsp-bf531/adsp-bf532/adsp-bf533 processors can be clocked by an external crystal, a sine wave input, or a buff- ered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl-compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the proce ssors include an on-chip oscilla- tor circuit, an external crysta l can be used. for fundamental frequency operation, use the circuit shown in figure 8 . a parallel-resonant, fundamental frequency, microprocessor- grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k ? range. further parallel resi stors are typically not rec- ommended. the two capacitors and the series resistor shown in figure 8 fine tune the phase and amplitude of the sine fre- quency. the capacitor and re sistor values shown in figure 8 are typical values only. the capaci tor values are dependent upon the crystal manufacturer's load capacitance recommendations and the physical pcb layout. the resistor value depends on the drive level specified by the crys tal manufacturer. system designs should verify the cust omized values based on careful investiga- tion on multiple devices over the allowed temperature range. a third-overtone crystal can be used at frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 8 . figure 7. voltage regulator circuit % power savings 1 power savings factor ? ?? 100% ? = v ddext (low-inductance) v ddint vr out 100f vr out gnd short and low- inductance wire v ddext + + + 100f 100f 10f low esr 100nf set of decoupling capacitors fds9431a zhcs1000 note: designer should minimize trace length to fds9431a. 10h figure 8. external crystal connections clkin clkout xtal en 18pf* 18pf* for overtone operation only v ddext to pll circuitry note: values marked with * must be customized depending on the crystal and layout. please analyze carefully. blackfin 700 : 0 : * 1m :
rev. i | page 14 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 as shown in figure 9 , the core clock ( cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a user programmable 0.5 ? to 64 ? multiplica- tion factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 10 ? , but it can be modified by a software inst ruction sequence. on-the-fly frequency changes can be effected by simply writing to the pll_div register. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. the maximum frequency of the system clock is f sclk . the divi- sor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynami- cally without any pll lock latenc ies by writing the appropriate values to the pll divisor register (pll_div). when the ssel value is changed, it affects all of the peripherals that derive their clock signals from the sclk signal. the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. booting modes the adsp-bf531/adsp-bf532/a dsp-bf533 processors have two mechanisms (listed in table 8 ) for automatically loading internal l1 instruction memory after a reset. a third mode is provided to execute from extern al memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory C execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). ? boot from 8-bit or 16-bit external flash memory C the flash boot routine located in boot rom memory space is set up using asynchronous memory ba nk 0. all configuration set- tings are set for the slowest de vice possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). ? boot from spi serial eeprom/flash (8-, 16-, or 24-bit addressable, or atmel at45db041, at45db081, or at45db161) C the spi uses the pf2 output pin to select a single spi eeprom/flash device, submits a read command and successive address bytes (0 x00) until a valid 8-, 16-, or 24-bit addressable eeprom/flash device is detected, and begins clocking data into the processor at the beginning of l1 instruction memory. ? boot from spi serial master C the blackfin processor oper- ates in spi slave mode and is configured to receive the bytes of the ldr file from an spi host (master) agent. to hold off the host device from transmitting while the boot rom is busy, the blackfin processor asserts a gpio pin, called host wait (hwait), to signal the host device not to send any figure 9. frequency mo dification methods table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0101 5:1 400 80 1010 10:1 500 50 pll 0.5 u to 64 u 1to15 1,2,4,8 vco clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk sclk d cclk sclk d 133 mhz table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 table 8. booting modes bmode1C0 description 00 execute from 16-bit external memory (bypass boot rom) 01 boot from 8-bit or 16-bit flash 10 boot from serial master connected to spi 11 boot from serial slave eeprom/flash (8-,16-, or 24- bit address range, or atmel at45db041, at45db081, or at45db161serial flash)
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 15 of 64 | august 2013 more bytes until the flag is deasserted. the gpio pin is chosen by the user and this information is transferred to the blackfin processor via bits[ 10:5] of the flag header in the ldr image. for each of the boot modes, a 10- byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks can be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, th e processor jumps directly to the beginning of l1 instruction memory. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/cpu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data ty pes; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development enviro nments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide vari ety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/ cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide incl udes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for crosscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed.
rev. i | page 16 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, fi le systems, usb stacks, and tcp/ ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the engineer-to-engineer note analog devices jtag emulation technical reference (ee-68) on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvemen ts to emulator support. additional information the following publications that describe the adsp-bf531/ adsp-bf532/adsp-bf533 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf533 blackfin proc essor hardware reference ? blackfin processor programming reference ? adsp-bf531/adsp-bf532/adsp-bf533 blackfin processor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 17 of 64 | august 2013 pin descriptions the adsp-bf531/adsp-bf532/ad sp-bf533 processors pin definitions are listed in table 9 . all pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. these pins are all driven high, with the exception of clkout, which toggles at the system clock rate. during hibernate, all outputs are three- stated unless otherwise noted in table 9 . if br is active (whether or not reset is asserted), the memory pins are also three-stated. all un used i/o pins have their input buffers disabled with the exception of the pins that need pull- ups or pull-downs as noted in the table. in order to maintain maximum functionality and reduce pack- age size and pin count, some pins have dual, multiplexed functionality. in cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate function- ality is shown in italics. table 9. pin descriptions pin name type function driver type 1 memory interface addr19C1 o address bus fo r async/sync access a data15C0 i/o data bus for async/sync access a abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a br i bus request (this pin should be pulled high if not used.) bg obus grant a bgh o bus grant hang a asynchronous memory control ams3C0 o bank select (require pull-u ps if hibernate is used.) a ardy i hardware ready control (this pin should be pulled high if not used.) aoe o output enable a are oread enable a awe owrite enable a synchronous memory control sras o row address strobe a scas o column address strobe a swe owrite enable a scke o clock enable (requires pull-down if hibernate is used.) a clkout o clock output b sa10 o a10 pin a sms o bank select a timers tmr0 i/o timer 0 c tmr1/ ppi_fs1 i/o timer 1/ ppi frame sync1 c tmr2/ ppi_fs2 i/o timer 2/ ppi frame sync2 c ppi port ppi3C0 i/o ppi3C0 c ppi_clk/ tmrclk i ppi clock/ external timer reference
rev. i | page 18 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 port f: gpio/parallel peripheral interface port/spi/timers pf0/ spiss i/o gpio/ spi slave select input c pf1 /spisel1 /taclk i/o gpio/ spi slave select enable 1/timer alternate clock input c pf2/ spisel2 i/o gpio/ spi slave select enable 2 c pf3/ spisel3 /ppi_fs3 i/o gpio/ spi slave select enable 3/ppi frame sync 3 c pf4/ spisel4 /ppi15 i/o gpio/ spi slave select enable 4/ppi 15 c pf5/ spisel5 /ppi14 i/o gpio/ spi slave select enable 5/ppi 14 c pf6/ spisel6 /ppi13 i/o gpio/ spi slave select enable 6/ppi 13 c pf7/ spisel7 /ppi12 i/o gpio/ spi slave select enable 7/ppi 12 c pf8/ ppi11 i/o gpio/ ppi 11 c pf9/ ppi10 i/o gpio/ ppi 10 c pf10/ ppi9 i/o gpio/ ppi 9 c pf11/ ppi8 i/o gpio/ ppi 8 c pf12/ ppi7 i/o gpio/ ppi 7 c pf13/ ppi6 i/o gpio/ ppi 6 c pf14/ ppi5 i/o gpio/ ppi 5 c pf15/ ppi4 i/o gpio/ ppi 4 c jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this pin should be pulled low if jtag is not used.) emu o emulation output c spi port mosi i/o master out slave in c miso i/o master in slave out (this pin should be pulled high through a 4.7 k ? resistor if booting via the spi port.) c sck i/o spi clock d serial ports rsclk0 i/o sport0 receive serial clock d rfs0 i/o sport0 receive frame sync c dr0pri i sport0 receive data primary dr0sec i sport0 receive data secondary tsclk0 i/o sport0 transmit serial clock d tfs0 i/o sport0 transmit frame sync c dt0pri o sport0 transmit data primary c dt0sec o sport0 transmit data secondary c rsclk1 i/o sport1 receive serial clock d table 9. pin descriptions (continued) pin name type function driver type 1
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 19 of 64 | august 2013 rfs1 i/o sport1 receive frame sync c dr1pri i sport1 receive data primary dr1sec i sport1 receive data secondary tsclk1 i/o sport1 transmit serial clock d tfs1 i/o sport1 transmit frame sync c dt1pri o sport1 transmit data primary c dt1sec o sport1 transmit data secondary c uart port rx i uart receive tx o uart transmit c real-time clock rtxi i rtc crystal input (this pin should be pulled low when not used.) rtxo o rtc crystal output (does not three-state in hibernate.) clock clkin i clock/crystal input (this pin needs to be at a level or clocking.) xtal o crystal output mode controls reset i reset (this pin is always active during core power-on.) nmi i nonmaskable interrupt (this pin should be pulled low when not used.) bmode1C0 i boot mode strap (these pins must be pulle d to the state required for the desired boot mode.) voltage regulator vrout1C0 o external fet drive (these pins should be left unconnected when unused and are driven high during hibernate.) supplies v ddext pi/o power supply v ddint p core power supply v ddrtc p real-time clock power supply (this pin should be connected to v ddext when not used and should remain powered at all times.) gnd g external ground 1 refer to figure 33 on page 43 to figure 44 on page 44 . table 9. pin descriptions (continued) pin name type function driver type 1
rev. i | page 20 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 specifications component specifications are subject to change without notice. operating conditions parameter conditions min nominal max unit v ddint internal supply voltage 1 1 the regulator can generate v ddint at levels of 0.85 v to 1.2 v with C5% to +10% tolerance, 1.25 v with C4% to +10% to lerance, and 1.3 v with C0% to +10% toleran ce. nonautomotive 400 mhz and 500 mhz speed grade models 2 2 see ordering guide on page 63 . 0.8 1.2 1.45 v v ddint internal supply voltage 1 nonautomotive 533 mhz speed grade models 2 0.8 1.25 1.45 v v ddint internal supply voltage 1 600 mhz speed grade models 2 0.8 1.30 1.45 v v ddint internal supply voltage 1 automotive 400 mhz speed grade models 2 0.95 1.2 1.45 v v ddint internal supply voltage 1 automotive 533 mhz speed grade models 2 0.95 1.25 1.45 v v ddext external supply voltage 3 3 when v ddext < 2.25 v, on-chip voltage regulation is not supported. nonautomotive grade models 2 1.75 1.8/3.3 3.6 v v ddext external supply voltage automotive grade models 2 2.7 3.3 3.6 v v ddrtc real-time clock power supply voltage nonautomotive grade models 2 1.75 1.8/3.3 3.6 v v ddrtc real-time clock power supply voltage automotive grade models 2 2.7 3.3 3.6 v v ih high level input voltage 4, 5 4 applies to all input and bidi rectional pins except clkin. 5 the adsp-bf531/adsp-bf532/adsp -bf533 processors are 3.3 v tolerant (always accepts up to 3.6 v maximum v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext , because v oh (maximum) approx imately equals v ddext (maximum). this 3.3 v tolerance applies to bidir ectional pins (data15C0, tmr2C0, pf 15C0, ppi3C0, rsclk1C0, tsclk1C0, rfs1C0, tfs1C0, mosi, miso, sck) and input only pins (br , ardy, ppi_clk, dr0pri, dr0sec, dr1pri, dr1sec, rx, rtxi, tck, tdi, tms, trst , clkin, reset , nmi, and bmode1C0). v ddext =1.85 v 1.3 v v ih high level input voltage 4, 5 v ddext =maximum 2.0 v v ihclkin high level input voltage 6 6 applies to clkin pin only. v ddext =maximum 2.2 v v il low level input voltage 7 7 applies to all input and bidirectional pins. v ddext =1.75 v +0.3 v v il low level input voltage 7 v ddext =2.7 v +0.6 v t j junction temperature 160-ball chip scale ball grid array (csp_bga) @ t ambient = 0c to +70c 0 +95 c t j junction temperature 160-ball chip scale ball grid array (csp_bga) @ t ambient = C40c to +85c C40 +105 c t j junction temperature 160-ball chip scale ball grid array (csp_bga) @ t ambient = C40c to +105c C40 +125 c t j junction temperature 169-ball plastic ball grid array (pbga) @ t ambient = C40c to +105c C40 +125 c t j junction temperature 169-ball plastic ball grid array (pbga) @ t ambient = C40c to +85c C40 +105 c t j junction temperature 176-lead quad flatpack (lqfp) @ t ambient = C40c to +85c C40 +100 c
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 21 of 64 | august 2013 the following three tables de scribe the voltage/frequency requirements for the processor clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock ( table 10 and table 11 ) and system clock ( table 13 ) specifications. table 12 describes phase-lock ed loop operating conditions. table 10. core clock (cclk) requirement s500 mhz, 533 mhz, and 600 mhz models parameter internal regulator setting max unit f cclk cclk frequency (v ddint = 1.3 v minimum) 1 1.30 v 600 mhz f cclk cclk frequency (v ddint = 1.2 v minimum) 2 1.25 v 533 mhz f cclk cclk frequency (v ddint = 1.14 v minimum) 3 1.20 v 500 mhz f cclk cclk frequency (v ddint = 1.045 v minimum) 1.10 v 444 mhz f cclk cclk frequency (v ddint = 0.95 v minimum) 1.00 v 400 mhz f cclk cclk frequency (v ddint = 0.85 v minimum) 0.90 v 333 mhz f cclk cclk frequency (v ddint = 0.8 v minimum) 0.85 v 250 mhz 1 applies to 600 mhz models only. see ordering guide on page 63 . 2 applies to 533 mhz and 60 0 mhz models only. see ordering guide on page 63 . 533 mhz models cannot support inte rnal regulator levels above 1.25 v. 3 applies to 500 mhz, 533 mh z, and 600 mhz models. see ordering guide on page 63 . 500 mhz models cannot support inter nal regulator levels above 1.20 v. table 11. core clock (cclk) requirements400 mhz models 1 parameter t j = 125c all 2 other t j unit internal regulator setting max max f cclk cclk frequency (v ddint = 1.14 v minimum) 1.20 v 400 400 mhz f cclk cclk frequency (v ddint = 1.045 v minimum) 1.10 v 333 364 mhz f cclk cclk frequency (v ddint = 0.95 v minimum) 1.00 v 295 333 mhz f cclk cclk frequency (v ddint = 0.85 v minimum) 0.90 v 280 mhz f cclk cclk frequency (v ddint = 0.8 v minimum) 0.85 v 250 mhz 1 see ordering guide on page 63 . 2 see operating conditions on page 20 . table 12. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 max f cclk mhz table 13. system clock (sclk) requirements v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter 1 max max unit csp_bga/pbga f sclk clkout/sclk frequency (v ddint ? 1.14 v) 100 133 mhz f sclk clkout/sclk frequency (v ddint ? 1.14 v) 100 100 mhz lqfp f sclk clkout/sclk frequency (v ddint ? 1.14 v) 100 133 mhz f sclk clkout/sclk frequency (v ddint ? 1.14 v) 83 83 mhz 1 t sclk (= 1/f sclk ) must be greater than or equal to t cclk .
rev. i | page 22 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 electrical characteristics 400 mhz 1 1 applies to all 400 mhz speed grade models. see ordering guide on page 63 . 500 mhz/533 mhz/600 mhz 2 2 applies to all 500 mhz, 533 mhz, and 600 mhz speed grade models. see ordering guide on page 63 . parameter test conditions min typical max min typical max unit v oh high level output voltage 3 3 applies to output an d bidirectional pins. v ddext = 1.75 v, i oh = C0.5 ma v ddext = 2.25 v, i oh = C0.5 ma v ddext = 3.0 v, i oh = C0.5 ma 1.5 1.9 2.4 1.5 1.9 2.4 v v v v ol low level output voltage 3 v ddext = 1.75 v, i ol = 2.0 ma v ddext = 2.25 v/3.0 v, i ol =2.0ma 0.2 0.4 0.2 0.4 v v i ih high level input current 4 4 applies to input pins except jtag inputs. v ddext = max, v in = v dd max 10.0 10.0 a i ihp high level input current jtag 5 v ddext = max, v in = v dd max 50.0 50.0 a i il 6 low level input current 4 v ddext = max, v in = 0 v 10.0 10.0 a i ozh three-state leakage current 7 v ddext = max, v in = v dd max 10.0 10.0 a i ozl 6 three-state leakage current 7 v ddext = max, v in = 0 v 10.0 10.0 a c in input capacitance 8 f in = 1 mhz, t ambient = 25c, v in = 2.5 v 48 9 48 9 pf i dddeepsleep 10 v ddint current in deep sleep mode v ddint = 1.0 v, f cclk = 0 mhz, t j = 25c, asf = 0.00 7.5 32.5 ma i ddsleep v ddint current in sleep mode v ddint = 0.8 v, t j = 25c, sclk = 25 mhz 10 37.5 ma i dd-typ 11 v ddint current v ddint = 1.14 v, f cclk = 400 mhz, t j = 25c 125 152 ma i dd-typ 11 v ddint current v ddint = 1.2 v, f cclk = 500 mhz, t j = 25c 190 ma i dd-typ 11 v ddint current v ddint = 1.2 v, f cclk = 533 mhz, t j = 25c 200 ma i dd-typ 11 v ddint current v ddint = 1.3 v, f cclk = 600 mhz, t j = 25c 245 ma i ddhibernate 10 v ddext current in hibernate state v ddext = 3.6 v, clkin = 0 mhz, t j = max, voltage regulator off (v ddint = 0 v) 50 100 50 100 ? a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25 c20 20 ? a i dddeepsleep 10 v ddint current in deep sleep mode f cclk = 0 mhz 6 table 15 16 table 14 ma i dd-int v ddint current f cclk > 0 mhz i dddeepsleep + ( table 17 ? asf) i dddeepsleep + ( table 17 ? asf) ma
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 23 of 64 | august 2013 system designers should refer to estimating power for the adsp-bf531/bf532/bf533 blackfin processors (ee-229) , which provides detailed information for optimizing designs for lowest power. all topics discussed in this section are described in detail in ee-229. total power dissi pation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 22 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 14 or table 15 ), and i ddint specifies the total power specification for the listed test condi- tions, including the dynamic comp onent as a function of voltage (v ddint ) and frequency ( table 17 ). the dynamic component is also su bject to an activity scaling factor (asf) which represents ap plication code running on the processor ( table 16 ). 5 applies to jtag input pins (tck, tdi, tms, trst) . 6 absolute value. 7 applies to three-statable pins. 8 applies to all signal pins. 9 guaranteed, but not tested. 10 see the adsp-bf533 blackfin process or hardware reference manual for definitions of sleep, deep sl eep, and hibernate operating modes. 11 see table 16 for the list of i ddint power vectors covered by various activity scaling factors (asf). table 14. static currentC500 mhz, 533 mhz, and 600 mhz speed grade devices (ma) 1 voltage (v ddint ) 2 t j (c) 2 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v 1.43 v 1.45 v C45 4.3 5.3 5.9 7.0 8.2 9.8 11.2 13.0 15.2 17.7 20.2 21.6 25.5 30.1 32.0 0 18.821.324.127.831.635.640.145.351.458.165.068.578.489.894.3 25 35.3 39.9 45.0 50.9 57.3 64.4 72.9 80.9 90.3 101.4 112.1 118.0 133.7 151.6 158.7 40 52.3 58.5 65.1 73.3 81.3 90.9 101.2 112.5 125.5 138.7 154.4 160.6 180.6 203.1 212.0 55 73.6 82.5 92.0 102.7 114.4 126.3 141.2 155.7 172.7 191.1 212.1 220.8 247.6 277.7 289.5 70 100.8 112.5 124.5 137.4 152.6 168.4 186.5 205.4 227.0 250.3 276.2 287.1 320.4 357.4 371.9 85 133.3 148.5 164.2 180.5 198.8 219.0 241.0 264.5 290.6 319.7 350.2 364.6 404.9 449.7 467.2 100 178.3 196.3 216.0 237.6 259.9 284.6 311.9 342.0 373.1 408.0 446.1 462.6 511.1 564.7 585.6 115 223.3 245.9 270.2 295.7 323.5 353.3 386.1 421.1 460.1 500.9 545.0 566.5 624.3 688.1 712.8 125 278.5 305.8 334.1 364.3 397.4 432.4 470.6 509.3 553.4 600.6 652.1 676.5 742.1 814.1 841.9 1 values are guaranteed maximum i dddeepsleep specifications. 2 valid temperature and voltage ranges are model-specific. see operating conditions on page 20 . table 15. static currentC400 mhz speed grade devices (ma) 1 voltage (v ddint ) 2 t j (c) 2 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1 .10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v C45 0.9 1.1 1.3 1.5 1.8 2.2 2.6 3.1 3.8 4.4 5.0 5.4 0 3.3 3.7 4.2 4.8 5.5 6.3 7.2 8.1 8.9 10.1 11.2 11.9 25 7.5 8.4 9.4 10.0 11.2 12.6 14.1 15.5 17.2 19.0 21.2 21.9 40 12.0 13.1 14.3 15.9 17.4 19.4 21.5 23.5 25.8 28.1 30.8 32.0 55 18.3 20.0 21.9 23.6 26.0 28.2 30.8 33.7 36.8 39.8 43.4 45.0 70 27.7 30.3 32.6 35.3 38.2 41.7 45.2 49.0 52.8 57.6 62.4 64.2 85 38.2 41.7 44.9 48.6 52.7 57.3 61.7 66.7 72.0 77.5 83.9 86.5 100 54.1 58.1 63.2 67.8 73.2 78.8 84.9 91.5 98.4 106.0 113.8 117.2 115 73.9 80.0 86.3 91.9 99.1 106.6 114.1 122.4 131.1 140.9 151.1 155.5 125 98.7 106.3 113.8 122.1 130.8 140.2 149.7 160.4 171.9 183.8 197.0 202.4 1 values are guaranteed maximum i dddeepsleep specifications. 2 valid temperature and voltage ranges are model-specific. see operating conditions on page 20 .
rev. i | page 24 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 table 16. activity scaling factors i ddint power vector 1 activity scaling factor (asf) 2 i dd-peak 1.27 i dd-high 1.25 i dd-typ 1.00 i dd-app 0.86 i dd-nop 0.72 i dd-idle 0.41 1 see ee-229 for power vector definitions. 2 all asf values determined using a 10:1 cclk:sclk ratio. table 17. dynamic current (ma, with asf = 1.0) 1 voltage (v ddint ) 2 frequency (mhz) 2 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v 1.43 v 1.45 v 50 12.7 13.9 15.3 16.8 18.1 19.4 21.0 22.3 24.0 25.4 26.4 27.2 28.7 30.3 30.7 100 22.6 24.2 26.2 28.1 30.1 31.8 34.7 36.2 38.4 40.5 43.0 43.4 45.7 47.9 48.9 200 40.8 44.1 46.9 50.3 53.3 56.9 59.9 63.1 66.7 70.2 73.8 75.0 78.7 82.4 84.6 250 50.1 53.8 57.2 61.4 64.7 68.9 72.9 76.8 81.0 85.1 89.3 90.8 95.2 99.6 102.0 300 n/a 63.5 67.4 72.4 76.2 81.0 85.9 90.6 95.2 100.0 104.8 106.6 111.8 116.9 119.4 375 n/a n/a n/a 88.6 93.5 99.0 104.6 110.3 116.0 122.1 128.0 130.0 136.2 142.4 145.5 400 n/a n/a n/a 93.9 99.3 105.0 110.8 116.8 123.0 129.4 135.7 137.9 144.6 151.2 154.3 425 n/a n/a n/a n/a n/a 111.0 117.3 123.5 129.9 136.8 143.2 145.6 152.6 159.7 162.8 475 n/a n/a n/a n/a n/a n/a 130.3 136.8 143.8 151.4 158.1 161.1 168.9 176.6 179.7 500 n/a n/a n/a n/a n/a n/a n/a 143.5 150.7 158.7 165.6 168.8 177.0 185.2 188.2 533 n/a n/a n/a n/a n/a n/a n/a n/a 160.4 168.8 176.5 179.6 188.2 196.8 200.5 600 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 196.2 199.6 209.3 219.0 222.6 1 the values are not guaranteed as stand-alone maximum specificatio ns, they must be combined with static current per the equation s of electrical characteristics on page 22 . 2 valid temperature and voltage ranges are model-specific. see operating conditions on page 20 .
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 25 of 64 | august 2013 absolute maximum ratings stresses greater than those listed in table 18 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods can affect device reliability. esd sensitivity table 18. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint ) C0.3 v to +1.45 v external (i/o) supply voltage (v ddext )C0.5 v to +3.8 v input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 19 . 2 applies only when v ddext is within specifications. when v ddext is outside speci- fications, the range is v ddext ? 0.2 v. C0.5 v to +3.8 v output voltage swing C0.5 v to v ddext + 0.5 v storage temperature range C65c to +150c junction temperature while biased 125c table 19. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with the exception of clkin, xtal, vrout1C0. v in min (v) 2 v in max (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. this is equivalent to the measured durati on of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.50 +3.80 100% C0.70 +4.00 40% C0.80 +4.10 25% C0.90 +4.20 15% C1.00 +4.30 10% esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
rev. i | page 26 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 package information the information presented in figure 10 and table 20 provides details about the package branding for the blackfin processors. for a complete listing of pr oduct availability, see the ordering guide on page 63 . figure 10. product information on package table 20. package br and information 1 1 non automotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description adsp-bf53x either adsp-bf531, adsp-bf532, or adsp-bf533 t temperature range pp package type z rohs compliant part ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppzccc adsp-bf53x a #yyww country_of_origin b
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 27 of 64 | august 2013 timing specifications clock and reset timing table 21 and figure 11 describe clock and reset operations. per absolute maximum ratings on page 25 , combinations of clkin and clock multipliers/divisors must not result in core/ system clocks exceeding the maximum limits allowed for the processor, including system cloc k restrictions related to supply voltage. table 21. clock and reset timing parameter min max unit timing requirements t ckin clkin period 1, 2, 3, 4 25.0 100.0 ns t ckinl clkin low pulse 10.0 ns t ckinh clkin high pulse 10.0 ns t wrst reset asserted pulse width low 5 11 ? t ckin ns t noboot reset deassertion to first external access delay 6 3 ? t ckin 5 ? t ckin ns 1 applies to pll bypass mode and pll non bypass mode. 2 clkin frequency must not change on the fly. 3 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 11 on page 21 through table 13 on page 21 . since the default behavior of the pll is to multiply the clki n frequency by 10, the 400 mhz speed grade parts cannot use the full clkin period range. 4 if the df bit in the pll_ctl register is set, then the maximum t ckin period is 50 ns. 5 applies after power-up se quence is complete. see table 22 and figure 12 for power-up reset timing. 6 applies when processor is configured in no boot mode (bmode1-0 = b#00). figure 11. clock and reset timing table 22. power-up reset timing parameter min max unit timing requirement t rst_in_pwr reset deasserted after the v ddint , v ddext , v ddrtc , and clkin pins are stable and within specification 3500 ? t ckin ns in figure 12 , v dd_supplies is v ddint , v ddext , v ddrtc figure 12. power -up reset timing clkin t wrst t ckin t ckinl t ckinh reset t noboot reset t rst_in_pwr clkin v dd_supplies
rev. i | page 28 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 asynchronous memory read cycle timing table 23. asynchronous memory read cycle timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t sdat data15C0 setup before clkout 2.1 2.1 ns t hdat data15C0 hold after clkout 1.0 0.8 ns t sardy ardy setup before clkout 4.0 4.0 ns t hardy ardy hold after clkout 1.0 0.0 ns switching characteristics t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe , are . 6.0 6.0 ns t ho output hold after clkout 1 1.0 0.8 ns figure 13. asynchronous memory read cycle timing t sardy t hardy t sardy t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t sdat t hdat clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 29 of 64 | august 2013 asynchronous memory write cycle timing table 24. asynchronous memory write cycle timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t sardy ardy setup before clkout 4.0 4.0 ns t hardy ardy hold after clkout 1.0 0.0 ns switching characteristics t ddat data15C0 disable after clkout 6.0 6.0 ns t endat data15C0 enable after clkout 1.0 1.0 ns t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6.0 6.0 ns t ho output hold after clkout 1 1.0 0.8 ns figure 14. asynchronous memory write cycle timing setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe data 15C0 t do t sardy t ddat t endat t ho t hardy t hardy ardy t sardy
rev. i | page 30 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 sdram interface timing table 25. sdram interface timing 1 1 sdram timing for t j > 105c is limited to 100 mhz. v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t ssdat data setup before clkout 2.1 1.5 ns t hsdat data hold after clkout 0.8 0.8 ns switching characteristics t dcad command, addr, data delay after clkout 2 2 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 6.0 4.0 ns t hcad command, addr, data hold after clkout 2 1.0 1.0 ns t dsdat data disable after clkout 6.0 4.0 ns t ensdat data enable after clkout 1.0 1.0 ns t sclk clkout period 3 3 refer to table 13 on page 21 for maximum f sclk at various v ddint . 10.0 7.5 ns t sclkh clkout width high 2.5 2.5 ns t sclkl clkout width low 2.5 2.5 ns figure 15. sdram interface timing t sclk clkout t sclkl t sclkh t ssdat t hsdat t ensdat t dcad t dsdat t hcad t dcad t hcad data (in) data (out) command, address (out) note: command = sras , scas , swe , sdqm, sms , sa10, scke.
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 31 of 64 | august 2013 external port bus request and grant cycle timing table 26 and figure 16 describe external port bus request and bus grant operations. table 26. external port bus request and grant cycle timing v ddext = 1.8 v lqfp/pbga packages v ddext = 1.8 v csp_bga package v ddext = 2.5 v/3.3 v all packages parameter min max min max min max unit timing requirements t bs br asserted to clkout high setup 4.6 4.6 4.6 ns t bh clkout high to br deasserted hold time 1.0 1.0 0.0 ns switching characteristics t sd clkout low to amsx , address, and are /awe disable 4.5 4.5 4.5 ns t se clkout low to amsx , address, and are /awe enable 4.5 4.5 4.5 ns t dbg clkout high to bg high setup 6.0 5.5 3.6 ns t ebg clkout high to bg deasserted hold time 6.0 4.6 3.6 ns t dbh clkout high to bgh high setup 6.0 5.5 3.6 ns t ebh clkout high to bgh deasserted hold time 6.0 4.6 3.6 ns figure 16. external port bus request and grant cycle timing amsx clkout bg bgh br addr 19-1 abe1-0 t bh t bs t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are
rev. i | page 32 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 parallel peripheral interface timing table 27 and figure 17 through figure 22 describe parallel peripheral interface operations. table 27. parallel peripheral interface timing v ddext = 1.8 v lqfp/pbga packages v ddext = 1.8 v csp_bga package v ddext = 2.5 v/3.3 v all packages parameter min max min max min max unit timing requirements t pclkw ppi_clk width 8.0 8.0 6.0 ns t pclk ppi_clk period 1 20.0 20.0 15.0 ns t sfspe external frame sync setup before ppi_clk edge (nonsampling edge for rx, sampling edge for tx) 6.0 6.0 4.0 2 ns ns t hfspe external frame sync hold after ppi_clk 1.0 2 1.0 2 1.0 2 ns t sdrpe receive data setup before ppi_clk 3.5 3.5 3.5 ns t hdrpe receive data hold after ppi_clk 1.5 1.5 1.5 ns switching characteristicsgp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 11.0 8.0 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 11.0 9.0 9.0 ns t hdtpe transmit data hold after ppi_clk 1.8 1.8 1.8 ns 1 ppi_clk frequency cannot exceed f sclk /2. 2 applies when ppi_control bit 8 is cleared. see figure 19 and figure 22 . figure 17. ppi gp rx mode with internal frame sync timing figure 18. ppi gp rx mode with external frame sync timing (p pi_control bit 8 = 1) t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 33 of 64 | august 2013 figure 19. ppi gp rx mode with external frame sync timing (p pi_control bit 8 = 0) figure 20. ppi gp tx mode with internal frame sync timing figure 21. ppi gp tx mode with external frame sync timing (ppi_control bit 8 = 1) figure 22. ppi gp tx mode with external frame sync timing (ppi_control bit 8 = 0) t pclk t sfspe frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw data sampled t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hdtpe t sfspe data driven frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw
rev. i | page 34 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 serial port timing table 28 through table 31 on page 37 and figure 23 on page 35 through figure 26 on page 37 describe serial port operations. table 28. serial portsexternal clock v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclkx 1 3.0 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclkx 1 3.0 3.0 ns t sdre receive data setup before rsclkx 1 3.0 3.0 ns t hdre receive data hold after rsclkx 1 3.0 3.0 ns t sclkew tsclkx/rsclkx width 8.0 4.5 ns t sclke tsclkx/rsclkx period 20.0 15.0 2 ns t sudte start-up delay from sport enable to first external tfsx 3 4.0 t sclke 4.0 t sclke ns t sudre start-up delay from sport enable to first external rfsx 3 4.0 t sclke 4.0 t sclke ns switching characteristics t dfse tfsx/rfsx delay after ts clkx/rsclkx (internally generated tfsx/rfsx) 4 10.0 10.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 1 0.0 0.0 ns t ddte transmit data delay after tsclkx 1 10.0 10.0 ns t hdte transmit data hold after tsclkx 1 0.0 0.0 ns 1 referenced to sample edge. 2 for receive mode with external rsclkx and external rfsx only, the maximum specification is 11.11 ns (90 mhz). 3 verified in design but untested. after bein g enabled, the serial port requires exte rnal clock pulsesbefore the first external frame sync edgeto initia lize the serial port. 4 referenced to drive edge. table 29. serial portsinternal clock v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.0 9.0 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 ? 2.0 ? 2.0 ns t sdri receive data setup before rsclkx 1 9.5 9.0 ns t hdri receive data hold after rsclkx 1 0.0 0.0 ns switching characteristics t dfsi tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 3.0 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 1 ? 1.0 ? 1.0 ns t ddti transmit data delay after tsclkx 1 3.0 3.0 ns t hdti transmit data hold after tsclkx 1 ? 2.5 ? 2.0 ns t sclkiw tsclkx/rsclkx width 6.0 4.5 ns 1 referenced to sample edge. 2 referenced to drive edge.
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 35 of 64 | august 2013 figure 23. serial ports figure 24. serial port start up with external clock and frame sync t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled
rev. i | page 36 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 table 30. serial portsenable and three-state v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit switching characteristics t dtene data enable delay from external tsclkx 1 00ns t ddtte data disable delay from external tsclkx 1, 2, 3 10.0 10.0 ns t dteni data enable delay from internal tsclkx 1 ? 2.0 ? 2.0 ns t ddtti data disable delay from internal tsclkx 1, 2, 3 3.0 3.0 ns 1 referenced to drive edge. 2 applicable to multi channel mode only. 3 tsclkx is tied to rsclkx. figure 25. enable and three-state tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 37 of 64 | august 2013 table 31. external late frame sync v ddext = 1.8 v lqfp/pbga packages v ddext = 1.8 v csp_bga package v ddext = 2.5 v/3.3 v all packages parameter min max min max min max unit switching characteristics t ddtlfse dat a d e l ay f ro m l at e e x te r na l t f sx o r e x te r n a l r fs x in multichannel mode with mcmen = 0 1, 2 10.5 10.0 10.0 ns t dtenlfs data enable from late fs or in multichannel mode with mcmen = 0 1, 2 000ns 1 in multichannel mode, tfsx en able and tfsx valid follow t dtenlfs and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2, then t ddtte/i and t dtene/i apply; otherwise t ddtlfse and t dtenlfs apply. figure 26. external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
rev. i | page 38 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 serial peripheral interface (spi) portmaster timing table 32. serial peripheral interface (spi) portmaster timing v ddext = 1.8 v lqfp/pbga packages v ddext = 1.8 v csp_bga package v ddext = 2.5 v/3.3 v all packages parameter min max min max min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 10.5 9 7.5 ns t hspidm sck sampling edge to data input invalid C1.5 C1.5 C1.5 ns switching characteristics t sdscim spiselx low to first sck edge 2 t sclk C 1.5 2 t sclk C 1.5 2 t sclk C 1.5 ns t spichm serial clock high period 2 t sclk C 1.5 2 t sclk C 1.5 2 t sclk C 1.5 ns t spiclm serial clock low period 2 t sclk C 1.5 2 t sclk C 1.5 2 t sclk C 1.5 ns t spiclk serial clock period 4 t sclk C 1.5 4 t sclk C 1.5 4 t sclk C 1.5 ns t hdsm last sck edge to spiselx high 2 t sclk C 1.5 2 t sclk C 1.5 2 t sclk C 1.5 ns t spitdm sequential transfer delay 2 t sclk C 1.5 2 t sclk C 1.5 2 t sclk C 1.5 ns t ddspidm sck edge to data out valid (data out delay) 6 6 6 ns t hdspidm sck edge to data out invalid (data out hold) C1.0 C1.0 C1.0 ns figure 27. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 39 of 64 | august 2013 serial peripheral interface (spi) portslave timing table 33. serial peripheral interface (spi) portslave timing v ddext = 1.8 v lqfp/pbga packages v ddext = 1.8 v csp_bga package v ddext = 2.5 v/3.3 v all packages parameter min max min max min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk 4 t sclk 4 t sclk ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 1.6 1.6 ns t hspid sck sampling edge to data input invalid 1.6 1.6 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 10 0 9 0 8 ns t dsdhi spiss deassertion to data high impedance 0 10 0 9 0 8 ns t ddspid sck edge to data out valid (data out delay) 10 10 10 ns t hdspid sck edge to data out invalid (data out hold) 0 0 0 ns figure 28. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
rev. i | page 40 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 general-purpose i/o port f pin cycle timing universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-bf533 blackfin processor hardware reference . table 34. general-purpose i/o port f pin cycle timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirement t wfi gpio input pulse width t sclk + 1 t sclk + 1 ns switching characteristic t gpod gpio output delay from clkout low 6 6 ns figure 29. gpio cycle timing clkout gpio output gpio input t wfi t gpod
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 41 of 64 | august 2013 timer clock timing table 35 and figure 30 describe timer clock timing. timer cycle timing table 36 and figure 31 describe timer expired operations. the input signal is asynchronous in width capture mode and exter- nal clock mode and has an absolute maximum input frequency of f sclk /2 mhz. table 35. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppi_clk high 12 ns figure 30. timer clock timing ppi_clk tmrx output t todp table 36. timer cycle timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing characteristics t wl timer pulse width low 1 1 t sclk 1 t sclk ns t wh timer pulse width high 1 1 t sclk 1 t sclk ns t tis timer input setup time before clkout low 2 8.0 6.5 ns t tih timer input hold time after clkout low 2 1.5 1.5 ns switching characteristic s t hto timer pulse width output 1 t sclk (2 32 C1) t sclk 1 t sclk (2 32 C1) t sclk ns t tod timer output update delay after clkout high 7.5 6.5 ns 1 the minimum pulse widths apply for tmrx input pins in width capture and external cl ock modes. they also apply to the pf1 or ppi _clk input pins in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 31. timer pw m_out cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto
rev. i | page 42 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 jtag test and emulation port timing table 37. jtag port timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing requirements t tck tck period 20 20 ns t stap tdi, tms setup before tck high 4 4 ns t htap tdi, tms hold after tck high 4 4 ns t ssys system inputs setup before tck high 1 1 system inputs = data15C0, ardy, tmr2C0, pf 15C0, ppi_clk, rsclk0C1, rfs0C1, dr0pri, dr0sec, tsclk0C1, tfs0C1, dr1pri, dr1sec, mo si, miso, sck, rx, reset , nmi, bmode1C0, br , ppi3C0. 44 ns t hsys system inputs hold after tck high 1 55 ns t trstw trst pulse width 2 (measured in tck cycles) 2 50 mhz maximum. 44 tck switching characteristics t dtdo tdo delay from tck low 10 10 ns t dsys system outputs delay after tck low 3 3 system outputs = data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , tmr2C0, pf15C0, rsclk0C1, rfs0C1, tsclk0C1, tfs0C1, dt0pri, dt0sec, dt1pri, dt1sec, mosi, miso, sck, tx, bg , bgh , ppi3C0. 012012ns figure 32. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 43 of 64 | august 2013 output drive currents figure 33 through figure 44 show typical current-voltage char- acteristics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. figure 33. drive current a (v ddext = 2.5 v) figure 34. drive current a (v ddext = 1.8 v) figure 35. drive current a (v ddext = 3.3 v) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v v ddext = 2.50v v ddext = 2.75v source voltage (v) 0 0.5 1.0 1.5 2.0 source current (ma) 80 60 40 20 0 C 20 C 40 C 60 C 80 v ddext = 1.9v v ddext = 1.8v v ddext = 1.7v source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 v oh v ddext = 2.95v v ddext = 3.30v v ddext = 3.65v v ol figure 36. drive current b (v ddext = 2.5 v) figure 37. drive current b (v ddext = 1.8 v) figure 38. drive current b (v ddext = 3.3 v) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v v ddext = 2.50v v ddext = 2.75v source voltage (v) 0 0.5 1.0 1.5 2.0 source current (ma) 80 60 40 20 0 C 20 C 40 C 60 C 80 v ddext = 1.9v v ddext = 1.8v v ddext = 1.7v v oh v ddext = 3.30v v ddext = 2.95v v ddext = 3.65v v ol source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source current (ma)
rev. i | page 44 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 figure 39. drive current c (v ddext = 2.5 v) figure 40. drive current c (v ddext = 1.8 v) figure 41. drive current c (v ddext = 3.3 v) source current (ma) source voltage (v) 60 40 20 0 C20 C40 C60 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v v ddext = 2.50v v ddext = 2.75v source voltage (v) 0 0.5 1.0 1.5 2.0 source current (ma) 30 20 0 C 20 C 30 C 40 v ddext = 1.9v v ddext = 1.8v v ddext = 1.7v 10 C 10 60 80 100 40 20 0 C20 C40 C60 C80 C100 source current (ma) v oh v ddext = 2.95v v ddext = 3.30v v ddext = 3.65v v ol 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source voltage (v) figure 42. drive current d (v ddext = 2.5 v) figure 43. drive current d (v ddext = 1.8 v) figure 44. drive current d (v ddext = 3.3 v) source current (ma) source voltage (v) 100 60 C60 20 C20 0 C40 40 C80 80 C100 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh v ol v ddext = 2.25v v ddext = 2.50v v ddext = 2.75v source voltage (v) 0 0.5 1.0 1.5 2.0 source current (ma) 60 40 20 0 C 20 C 40 C 60 v ddext = 1.9v v ddext = 1.8v v ddext = 1.7v 150 100 50 0 C50 C100 C150 source current (ma) v oh v ol 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 source voltage (v) v ddext = 2.95v v ddext = 3.30v v ddext = 3.65v
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 45 of 64 | august 2013 test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 45 shows the measurement point for ac measurements (except out- put enable/disable). th e measurement point v meas is 0.95 v for v ddext (nominal) = 1.8 v or 1.5 v for v ddext (nominal) = 2.5 v/ 3.3 v. output enable time measurement output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 46 . the time t ena_measured is the interval, from when the reference signal switches, to when the output voltage reaches v trip (high) or v trip (low). for v ddext (nominal) = 1.8 vv trip (high) is 1.3 v and v trip (low) is 0.7 v. for v ddext (nominal) = 2.5 v/3.3 vv trip (high) is 2.0 v and v trip (low) is 1.0 v. time t trip is the interval from when the output starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the da ta bus) are enabled, the measure- ment value is that of the first pin to start driving. output disable time measurement output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis_measured and t decay as shown on the left side of figure 45 . the time for the voltage on the bus to decay by ? v is dependent on the capacitive load c l and the load current i i . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with ? v equal to 0.1 v for v ddext (nominal) = 1.8 v or 0.5 v for v ddext (nominal) = 2.5 v/3.3 v. the time t dis_measured is the interval from when the reference signal switches, to when the output voltage decays ? v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leak- age or three-state current (per data line). the hold time is t decay plus the various output disable times as specified in the timing specifications on page 27 (for example t dsdat for an sdram write cycle as shown in sdram interface timing on page 30 ). figure 45. voltage reference levels for ac measurements (except output enable/disable) input or output v meas v meas t ena t ena_measured t trip ? = t dis t dis_measured t decay ? = t decay c l v ? ?? i l ? = figure 46. output enable/disable reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low)
rev. i | page 46 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 capacitive loading output delays and holds are based on standard capa citive loads: 30 pf on all pins (see figure 47 ). v load is 0.95 v for v ddext (nominal) = 1.8 v or 1.5 v for v ddext (nominal) = 2.5 v/3.3 v. figure 48 through figure 59 on page 48 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear out- side the ranges shown. figure 47. equivalent device loading for ac measurements (includes all fixtures) t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 rise time fall time load capacitance (pf) 0 50 100 150 200 250 16 14 12 10 8 6 4 2 0 rise and fall time ns (10% to 90%) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 47 of 64 | august 2013 figure 51. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 1.75 v figure 52. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 2.25 v figure 53. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 3.65 v rise time fall time load capacitance (pf) 0 50 100 150 200 250 rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time figure 54. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 1.75 v figure 55. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 2.25 v figure 56. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 3.65 v rise time fall time load capacitance (pf) 0 50 100 150 200 250 30 25 20 15 10 5 0 rise and fall time ns (10% to 90%) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 25 30 20 15 10 5 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
rev. i | page 48 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 figure 57. typical rise and fall times (10% to 90%) vs. load capacitance for driver d at v ddext = 1.75 v figure 58. typical rise and fall times (10% to 90%) vs. load capacitance for driver d at v ddext = 2.25 v figure 59. typical rise and fall times (10% to 90%) vs. load capacitance for driver d at v ddext = 3.65 v rise time fall time sck (66mhz driver), v ddext = 1.7v load capacitance (pf) 0 50 100 150 200 250 18 16 14 12 10 8 6 4 2 0 rise and fall time ns (10% to 90%) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 49 of 64 | august 2013 thermal characteristics to determine the junction te mperature on the application printed circuit board, use: where: t j = junction temperature ( c). t case = case temperature ( c) measured by customer at top center of package. ? jt = from table 38 through table 40 . p d = power dissipation (see the power dissipation discussion and the tables on 23 for the method to calculate p d ). values of ? ja are provided for package comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature ( c). in table 38 through table 40 , airflow measurements comply with jedec standard s jesd51C2 and jesd51C6, and the junc- tion-to-board measurement co mplies with jesd51C8. the junction-to-case measuremen t complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. thermal resistance ? ja in table 38 through table 40 is the figure of merit relating to performanc e of the package and board in a convective environment. ? jma represents the thermal resistance under two conditions of airflow. ? jt represents the correlation between t j and t case . t j t case ? jt p d ? ?? + = t j t a ? ja p d ? ?? + = table 38. thermal characteristics for bc-160 package parameter condition typical unit ? ja 0 linear m/s airflow 27.1 c/w ? jma 1 linear m/s airflow 23.85 c/w ? jma 2 linear m/s airflow 22.7 c/w ? jc not applicable 7.26 c/w ? jt 0 linear m/s airflow 0.14 c/w ? jt 1 linear m/s airflow 0.26 c/w ? jt 2 linear m/s airflow 0.35 c/w table 39. thermal characterist ics for st-176-1 package parameter condition typical unit ? ja 0 linear m/s airflow 34.9 c/w ? jma 1 linear m/s airflow 33.0 c/w ? jma 2 linear m/s airflow 32.0 c/w ? jt 0 linear m/s airflow 0.50 c/w ? jt 1 linear m/s airflow 0.75 c/w ? jt 2 linear m/s airflow 1.00 c/w table 40. thermal characteristics for b-169 package parameter condition typical unit ? ja 0 linear m/s airflow 22.8 c/w ? jma 1 linear m/s airflow 20.3 c/w ? jma 2 linear m/s airflow 19.3 c/w ? jc not applicable 10.39 c/w ? jt 0 linear m/s airflow 0.59 c/w ? jt 1 linear m/s airflow 0.88 c/w ? jt 2 linear m/s airflow 1.37 c/w
rev. i | page 50 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 160-ball csp_bga ball assignment table 41 lists the csp_bga ball assignment by signal. table 42 on page 51 lists the csp_bga ball assignment by ball number. table 41. 160-ball csp_bga ball assign ment (alphabetical by signal) signal ball no. signal ball no. signal ball no. signal ball no. abe0 h13 data4 n8 gnd l6 sck d1 abe1 h12 data5 p8 gnd l8 scke b13 addr1 j14 data6 m7 gnd l10 sms c13 addr2 k14 data7 n7 gnd m4 sras d13 addr3 l14 data8 p7 gnd m10 swe d12 addr4 j13 data9 m6 gnd p14 tck p2 addr5 k13 data10 n6 miso e2 tdi m3 addr6 l13 data11 p6 mosi d3 tdo n3 addr7 k12 data12 m5 nmi b10 tfs0 h3 addr8 l12 data13 n5 pf0 d2 tfs1 e1 addr9 m12 data14 p5 pf1 c1 tmr0 l2 addr10 m13 data15 p4 pf2 c2 tmr1 m1 addr11 m14 dr0pri k1 pf3 c3 tmr2 k2 addr12 n14 dr0sec j2 pf4 b1 tms n2 addr13 n13 dr1pri g3 pf5 b2 trst n1 addr14 n12 dr1sec f3 pf6 b3 tsclk0 j1 addr15 m11 dt0pri h1 pf7 b4 tsclk1 f1 addr16 n11 dt0sec h2 pf8 a2 tx k3 addr17 p13 dt1pri f2 pf9 a3 v ddext a1 addr18 p12 dt1sec e3 pf10 a4 v ddext c7 addr19 p11 emu m2 pf11 a5 v ddext c12 ams0 e14 gnd a10 pf12 b5 v ddext d5 ams1 f14 gnd a14 pf13 b6 v ddext d9 ams2 f13 gnd b11 pf14 a6 v ddext f12 ams3 g12 gnd c4 pf15 c6 v ddext g4 aoe g13 gnd c5 ppi_clk c9 v ddext j4 ardy e13 gnd c11 ppi0 c8 v ddext j12 are g14 gnd d4 ppi1 b8 v ddext l7 awe h14 gnd d7 ppi2 a7 v ddext l11 bg p10 gnd d8 ppi3 b7 v ddext p1 bgh n10 gnd d10 reset c10 v ddint d6 bmode0 n4 gnd d11 rfs0 j3 v ddint e4 bmode1 p3 gnd f4 rfs1 g2 v ddint e11 br d14 gnd f11 rsclk0 l1 v ddint j11 clkin a12 gnd g11 rsclk1 g1 v ddint l4 clkout b14 gnd h4 rtxi a9 v ddint l9 data0 m9 gnd h11 rtxo a8 v ddrtc b9 data1 n9 gnd k4 rx l3 vrout0 a13 data2 p9 gnd k11 sa10 e12 vrout1 b12 data3 m8 gnd l5 scas c14 xtal a11
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 51 of 64 | august 2013 table 42. 160-ball csp_bga ball assign ment (numerical by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a1 v ddext c13 sms h1 dt0pri m3 tdi a2 pf8 c14 scas h2 dt0sec m4 gnd a3 pf9 d1 sck h3 tfs0 m5 data12 a4 pf10 d2 pf0 h4 gnd m6 data9 a5 pf11 d3 mosi h11 gnd m7 data6 a6 pf14 d4 gnd h12 abe1 m8 data3 a7 ppi2 d5 v ddext h13 abe0 m9 data0 a8 rtxo d6 v ddint h14 awe m10 gnd a9 rtxi d7 gnd j1 tsclk0 m11 addr15 a10 gnd d8 gnd j2 dr0sec m12 addr9 a11 xtal d9 v ddext j3 rfs0 m13 addr10 a12 clkin d10 gnd j4 v ddext m14 addr11 a13 vrout0 d11 gnd j11 v ddint n1 trst a14 gnd d12 swe j12 v ddext n2 tms b1 pf4 d13 sras j13 addr4 n3 tdo b2 pf5 d14 br j14 addr1 n4 bmode0 b3 pf6 e1 tfs1 k1 dr0pri n5 data13 b4 pf7 e2 miso k2 tmr2 n6 data10 b5 pf12 e3 dt1sec k3 tx n7 data7 b6 pf13 e4 v ddint k4 gnd n8 data4 b7 ppi3 e11 v ddint k11 gnd n9 data1 b8 ppi1 e12 sa10 k12 addr7 n10 bgh b9 v ddrtc e13 ardy k13 addr5 n11 addr16 b10 nmi e14 ams0 k14 addr2 n12 addr14 b11 gnd f1 tsclk1 l1 rsclk0 n13 addr13 b12 vrout1 f2 dt1pri l2 tmr0 n14 addr12 b13 scke f3 dr1sec l3 rx p1 v ddext b14 clkout f4 gnd l4 v ddint p2 tck c1 pf1 f11 gnd l5 gnd p3 bmode1 c2 pf2 f12 v ddext l6 gnd p4 data15 c3 pf3 f13 ams2 l7 v ddext p5 data14 c4 gnd f14 ams1 l8 gnd p6 data11 c5 gnd g1 rsclk1 l9 v ddint p7 data8 c6 pf15 g2 rfs1 l10 gnd p8 data5 c7 v ddext g3 dr1pri l11 v ddext p9 data2 c8 ppi0 g4 v ddext l12 addr8 p10 bg c9 ppi_clk g11 gnd l13 addr6 p11 addr19 c10 reset g12 ams3 l14 addr3 p12 addr18 c11 gnd g13 aoe m1 tmr1 p13 addr17 c12 v ddext g14 are m2 emu p14 gnd
rev. i | page 52 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 figure 60 shows the top view of the csp_bga ball configura- tion. figure 61 shows the bottom view of the csp_bga ball configuration. figure 60. 160-ball csp_bga ground configuration (top view) a b c d e f g h j k l m n p 12 345 678 91011121314 v ddint v ddext gnd i/o key: v rout v ddrtc figure 61. 160-ball csp_bga ground configuration (bottom view) a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ddint v ddext gnd i/o key: v rout v ddrtc
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 53 of 64 | august 2013 169-ball pbga ball assignment table 43 lists the pbga ball a ssignment by signal. table 44 on page 54 lists the pbga ball assignment by ball number. table 43. 169-ball pbga ball assign ment (alphabetical by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. abe0 h16data4u12gndk9 rtxia10v ddext k6 abe1 h17data5u11gndk10 rtxoa11v ddext l6 addr1 j16 data6 t10 gnd k11 rx t1 v ddext m6 addr2 j17 data7 u10 gnd l7 sa10 b15 v ddext m7 addr3 k16 data8 t9 gnd l8 scas a16 v ddext m8 addr4 k17 data9 u9 gnd l9 sck d1 v ddext t2 addr5 l16 data10 t8 gnd l10 scke b14 vrout0 b12 addr6 l17 data11 u8 gnd l11 sms a17 vrout1 b13 addr7 m16 data12 u7 gnd m9 sras a15 xtal a13 addr8 m17 data13 t7 gnd t16 swe b17 addr9 n17 data14 u6 miso e2 tck u4 addr10 n16 data15 t6 mosi e1 tdi u3 addr11 p17 dr0pri m2 nmi b11 tdo t4 addr12 p16 dr0sec m1 pf0 d2 tfs0 l1 addr13 r17 dr1pri h1 pf1 c1 tfs1 g2 addr14 r16 dr1sec h2 pf2 b1 tmr0 r1 addr15 t17 dt0pri k2 pf3 c2 tmr1 p2 addr16 u15 dt0sec k1 pf4 a1 tmr2 p1 addr17 t15 dt1pri f1 pf5 a2 tms t3 addr18 u16 dt1sec f2 pf6 b3 trst u2 addr19 t14 emu u1 pf7 a3 tsclk0 l2 ams0 d17 gnd b16 pf8 b4 tsclk1 g1 ams1 e16gndf11pf9 a4 tx r2 ams2 e17 gnd g7 pf10 b5 vdd f12 ams3 f16 gnd g8 pf11 a5 vdd g12 aoe f17 gnd g9 pf12 a6 vdd h12 ardy c16 gnd g10 pf13 b6 vdd j12 are g16 gnd g11 pf14 a7 vdd k12 awe g17 gnd h7 pf15 b7 vdd l12 bg t13 gnd h8 ppi_clk b10 vdd m10 bgh u17 gnd h9 ppi0 b9 vdd m11 bmode0 u5 gnd h10 ppi1 a9 vdd m12 bmode1 t5 gnd h11 ppi2 b8 v ddext b2 br c17 gnd j7 ppi3 a8 v ddext f6 clkin a14 gnd j8 reset a12 v ddext f7 clkout d16 gnd j9 rfs0 n1 v ddext f8 data0 u14 gnd j10 rfs1 j1 v ddext f9 data1 t12 gnd j11 rsclk0 n2 v ddext g6 data2 u13 gnd k7 rsclk1 j2 v ddext h6 data3 t11 gnd k8 rtcvdd f10 v ddext j6
rev. i | page 54 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 table 44. 169-ball pbga ball assignme nt (numerical by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 pf4 d16 clkout j2 rsclk1 m12 vdd u9 data9 a2 pf5 d17 ams0 j6 v ddext m16 addr7 u10 data7 a3 pf7 e1 mosi j7 gnd m17 addr8 u11 data5 a4 pf9 e2 miso j8 gnd n1 rfs0 u12 data4 a5 pf11 e16 ams1 j9 gnd n2 rsclk0 u13 data2 a6 pf12 e17 ams2 j10 gnd n16 addr10 u14 data0 a7 pf14 f1 dt1pri j11 gnd n17 addr9 u15 addr16 a8 ppi3 f2 dt1sec j12 vdd p1 tmr2 u16 addr18 a9 ppi1 f6 v ddext j16 addr1 p2 tmr1 u17 bgh a10 rtxi f7 v ddext j17 addr2 p16 addr12 a11 rtxo f8 v ddext k1 dt0sec p17 addr11 a12 reset f9 v ddext k2 dt0pri r1 tmr0 a13 xtal f10 rtcvdd k6 v ddext r2 tx a14 clkin f11 gnd k7 gnd r16 addr14 a15 sras f12 vdd k8 gnd r17 addr13 a16 scas f16 ams3 k9 gnd t1 rx a17 sms f17 aoe k10 gnd t2 v ddext b1 pf2 g1 tsclk1 k11 gnd t3 tms b2 v ddext g2 tfs1 k12 vdd t4 tdo b3 pf6 g6 v ddext k16 addr3 t5 bmode1 b4 pf8 g7 gnd k17 addr4 t6 data15 b5 pf10 g8 gnd l1 tfs0 t7 data13 b6 pf13 g9 gnd l2 tsclk0 t8 data10 b7 pf15 g10 gnd l6 v ddext t9 data8 b8 ppi2 g11 gnd l7 gnd t10 data6 b9 ppi0 g12 vdd l8 gnd t11 data3 b10 ppi_clk g16 are l9 gnd t12 data1 b11 nmi g17 awe l10 gnd t13 bg b12 vrout0 h1 dr1pri l11 gnd t14 addr19 b13 vrout1 h2 dr1sec l12 vdd t15 addr17 b14 scke h6 v ddext l16 addr5 t16 gnd b15 sa10 h7 gnd l17 addr6 t17 addr15 b16 gnd h8 gnd m1 dr0sec u1 emu b17 swe h9 gnd m2 dr0pri u2 trst c1 pf1 h10 gnd m6 v ddext u3 tdi c2 pf3 h11 gnd m7 v ddext u4 tck c16 ardy h12 vdd m8 v ddext u5 bmode0 c17 br h16 abe0 m9 gnd u6 data14 d1 sck h17 abe1 m10 vdd u7 data12 d2 pf0 j1 rfs1 m11 vdd u8 data11
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 55 of 64 | august 2013 figure 62. 169-ball pbga ground configuration (top view) figure 63. 169-ball pbga ground configuration (bottom view) a1 ball pad corner top view a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 v ddint v ddext gnd nc i/o v rout key a1 ball pad corner bottom view a b c d e f g h j k l m n p r t u 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 key: v ddint gnd nc v ddext i/o v rout
rev. i | page 56 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 176-lead lqfp pinout table 45 lists the lqfp pi nout by signal. table 46 on page 57 lists the lqfp pinout by lead number. table 45. 176-lead lqfp pin assign ment (alphabetical by signal) signal lead no. signal lead no. signal lead no. signal lead no. signal lead no. abe0 151 data3 113 gnd 88 ppi_clk 21 v ddext 71 abe1 150 data4 112 gnd 89 ppi0 22 v ddext 93 addr1 149 data5 110 gnd 90 ppi1 23 v ddext 107 addr2 148 data6 109 gnd 91 ppi2 24 v ddext 118 addr3 147 data7 108 gnd 92 ppi3 26 v ddext 134 addr4 146 data8 105 gnd 97 reset 13 v ddext 145 addr5 142 data9 104 gnd 106 rfs0 75 v ddext 156 addr6 141 data10 103 gnd 117 rfs1 64 v ddext 171 addr7 140 data11 102 gnd 128 rsclk0 76 v ddint 25 addr8 139 data12 101 gnd 129 rsclk1 65 v ddint 52 addr9 138 data13 100 gnd 130 rtxi 17 v ddint 66 addr10 137 data14 99 gnd 131 rtxo 16 v ddint 80 addr11 136 data15 98 gnd 132 rx 82 v ddint 111 addr12 135 dr0pri 74 gnd 133 sa10 164 v ddint 143 addr13 127 dr0sec 73 gnd 144 scas 166 v ddint 157 addr14 126 dr1pri 63 gnd 155 sck 53 v ddint 168 addr15 125 dr1sec 62 gnd 170 scke 173 v ddrtc 18 addr16 124 dt0pri 68 gnd 174 sms 172 vrout0 5 addr17 123 dt0sec 67 gnd 175 sras 167 vrout1 4 addr18 122 dt1pri 59 gnd 176 swe 165 xtal 11 addr19 121 dt1sec 58 miso 54 tck 94 ams0 161 emu 83 mosi 55 tdi 86 ams1 160 gnd 1 nmi 14 tdo 87 ams2 159 gnd 2 pf0 51 tfs0 69 ams3 158 gnd 3 pf1 50 tfs1 60 aoe 154 gnd 7 pf2 49 tmr0 79 ardy 162 gnd 8 pf3 48 tmr1 78 are 153 gnd 9 pf4 47 tmr2 77 awe 152 gnd 15 pf5 46 tms 85 bg 119 gnd 19 pf6 38 trst 84 bgh 120 gnd 30 pf7 37 tsclk0 72 bmode0 96 gnd 39 pf8 36 tsclk1 61 bmode1 95 gnd 40 pf9 35 tx 81 br 163 gnd 41 pf10 34 v ddext 6 clkin 10 gnd 42 pf11 33 v ddext 12 clkout 169 gnd 43 pf12 32 v ddext 20 data0 116 gnd 44 pf13 29 v ddext 31 data1 115 gnd 56 pf14 28 v ddext 45 data2 114 gnd 70 pf15 27 v ddext 57
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 57 of 64 | august 2013 table 46. 176-lead lqfp pin assignme nt (numerical by lead number) lead no. signal lead no. signal lead no. signal lead no. signal lead no. signal 1 gnd 41 gnd 81 tx 121 addr19 161 ams0 2 gnd 42 gnd 82 rx 122 addr18 162 ardy 3gnd43gnd83emu 123 addr17 163 br 4 vrout1 44 gnd 84 trst 124 addr16 164 sa10 5vrout045v ddext 85 tms 125 addr15 165 swe 6v ddext 46 pf5 86 tdi 126 addr14 166 scas 7 gnd 47 pf4 87 tdo 127 addr13 167 sras 8 gnd 48 pf3 88 gnd 128 gnd 168 v ddint 9 gnd 49 pf2 89 gnd 129 gnd 169 clkout 10 clkin 50 pf1 90 gnd 130 gnd 170 gnd 11 xtal 51 pf0 91 gnd 131 gnd 171 v ddext 12 v ddext 52 v ddint 92 gnd132 gnd172 sms 13 reset 53 sck 93 v ddext 133 gnd 173 scke 14 nmi 54 miso 94 tck 134 v ddext 174 gnd 15 gnd 55 mosi 95 bmode1 135 addr12 175 gnd 16 rtxo 56 gnd 96 bmode0 136 addr11 176 gnd 17 rtxi 57 v ddext 97 gnd 137 addr10 18 v ddrtc 58 dt1sec 98 data15 138 addr9 19 gnd 59 dt1pri 99 data14 139 addr8 20 v ddext 60 tfs1 100 data13 140 addr7 21 ppi_clk 61 tsclk1 101 data12 141 addr6 22 ppi0 62 dr1sec 102 data11 142 addr5 23 ppi1 63 dr1pri 103 data10 143 v ddint 24 ppi2 64 rfs1 104 data9 144 gnd 25 v ddint 65 rsclk1 105 data8 145 v ddext 26 ppi3 66 v ddint 106 gnd 146 addr4 27 pf15 67 dt0sec 107 v ddext 147 addr3 28 pf14 68 dt0pri 108 data7 148 addr2 29 pf13 69 tfs0 109 data6 149 addr1 30 gnd 70 gnd 110 data5 150 abe1 31 v ddext 71 v ddext 111 v ddint 151 abe0 32 pf12 72 tsclk0 112 data4 152 awe 33 pf11 73 dr0sec 113 data3 153 are 34 pf10 74 dr0pri 114 data2 154 aoe 35 pf9 75 rfs0 115 data1 155 gnd 36 pf8 76 rsclk0 116 data0 156 v ddext 37 pf7 77 tmr2 117 gnd 157 v ddint 38 pf6 78 tmr1 118 v ddext 158 ams3 39 gnd 79 tmr0 119 bg 159 ams2 40 gnd 80 v ddint 120 bgh 160 ams1
rev. i | page 58 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 outline dimensions dimensions in the outline dimension figures are shown in millimeters. figure 64. 176-lead low profile quad flat package [lqfp] (st-176-1) dimensions shown in millimeters compliant to jedec standards ms-026-bga top view (pins down) 133 1 132 45 44 88 89 176 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 26.20 26.00 sq 25.80 24.20 24.00 sq 23.80
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 59 of 64 | august 2013 figure 65. 160-ball chip scale package ball grid array [csp_bga] (bc-160-2) dimensions shown in millimeters 0.80 bsc a b c d e f g 98 11 10 13 12 7 6 5 4 2 31 bottom view 10.40 bsc sq h j k l m n p 0.40 nom 0.25 min detail a top view detail a coplanarity 0.12 * 0.55 0.45 0.40 ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball corner a1 ball corner 1.70 1.60 1.35 1.31 1.21 1.11 14 * compliant to jedec standards mo-205-ae with the exception to ball diameter.
rev. i | page 60 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 figure 66. 169-ball plastic ball grid array [pbga] (b-169) dimensions shown in millimeters compliant to jedec standards ms-034-aag-2 17.05 16.95 sq 16.85 1.00 bsc 16.00 bsc sq a b c d e f g h j k l m n p r t u 1 2 3 4 6 8 10 11 12 13 14 15 16 5 7 9 17 top view seating plane 1.22 1.17 1.12 0.20 max coplanarity 0.65 0.56 0.45 detail a 0.70 0.60 0.50 ball diameter bottom view detail a a1 corner index area a1 ball pad indicator 2.50 2.23 1.97 19.20 19.00 sq 18.80 0.50 nom 0.40 min
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 61 of 64 | august 2013 surface-mount design table 47 is provided as an aid to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surfac e-mount design and land pat- tern standard . table 47. bga data for use with surface-mount design package ball attach type solder mask opening ball pad size chip scale package ball grid array (csp_bga) bc-160-2 solder mask defined 0.40 mm diameter 0.55 mm diameter plastic ball grid array (pbga) b-169 solder mask defined 0.43 mm diameter 0.56 mm diameter
rev. i | page 62 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 automotive products the adbf531w, adbf532w, an d adbf533w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models an d designers should review the specifications section of this data sheet carefully. only the auto- motive grade products shown in table 48 are available for use in automotive applications. contac t your local adi account repre- sentative for specific product ordering information and to obtain the specific automotive reliability reports for these models. table 48. automotive products product family 1,2 temperature range 3 speed grade (max) package description package option adbf531wbstz4xx C40 c to +85 c 400 mhz 176-lead lqfp st-176-1 adbf531wbbcz4xx C40 c to +85 c 400 mhz 160-ball csp_bga bc-160-2 adbf531wybcz4xx C40 c to +105 c 400 mhz 160-ball csp_bga bc-160-2 adbf532wbstz4xx C40 c to +85 c 400 mhz 176-lead lqfp st-176-1 adbf532wbbcz4xx C40 c to +85 c 400 mhz 160-ball csp_bga bc-160-2 adbf532wybcz4xx C40 c to +105 c 400 mhz 160-ball csp_bga bc-160-2 adbf533wbbcz5xx C40 c to +85 c 533 mhz 160-ball csp_bga bc-160-2 adbf533wbbz5xx C40 c to +85 c 533 mhz 169-ball pbga b-169 adbf533wybcz4xx C40 c to +105 c 400 mhz 160-ball csp_bga bc-160-2 ADBF533WYBBZ4xx C40 c to +105 c 400 mhz 169-ball pbga b-169 1 z = rohs compliant part. 2 xx denotes silicon revision. 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 20 for junction temperature (t j ) specification which is the on ly temperature specification.
adsp-bf531 / adsp-bf532 / adsp-bf533 rev. i | page 63 of 64 | august 2013 ordering guide model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 20 for junction temperature (t j ) specification which is the on ly temperature specification. speed grade (max) package description package option adsp-bf531sbb400 C40c to +85c 400 mhz 169-ball pbga b-169 adsp-bf531sbbz400 C40c to +85c 400 mhz 169-ball pbga b-169 adsp-bf531sbbc400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf531sbbcz400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf531sbbcz4rl C40c to +85c 400 mhz 160-ball csp_bga, 13" tape and reel bc-160-2 adsp-bf531sbstz400 C40c to +85c 400 mhz 176-lead lqfp st-176-1 adsp-bf532sbbz400 C40c to +85c 400 mhz 169-ball pbga b-169 adsp-bf532sbbc400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf532sbbcz400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf532sbstz400 C40c to +85c 400 mhz 176-lead lqfp st-176-1 adsp-bf533sbbz400 C40c to +85c 400 mhz 169-ball pbga b-169 adsp-bf533sbbc400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf533sbbcz400 C40c to +85c 400 mhz 160-ball csp_bga bc-160-2 adsp-bf533sbstz400 C40c to +85c 400 mhz 176-lead lqfp st-176-1 adsp-bf533sbb500 C40c to +85c 500 mhz 169-ball pbga b-169 adsp-bf533sbbz500 C40c to +85c 500 mhz 169-ball pbga b-169 adsp-bf533sbbc500 C40c to +85c 500 mhz 160-ball csp_bga bc-160-2 adsp-bf533sbbcz500 C40c to +85c 500 mhz 160-ball csp_bga bc-160-2 adsp-bf533sbbc-5v C40c to +85c 533 mhz 160-ball csp_bga bc-160-2 adsp-bf533sbbcz-5v C40c to +85c 533 mhz 160-ball csp_bga bc-160-2 adsp-bf533skbc-6v 0c to +70c 600 mhz 160-ball csp_bga bc-160-2 adsp-bf533skbcz-6v 0c to +70c 600 mhz 160-ball csp_bga bc-160-2 adsp-bf533skstz-5v 0c to +70c 533 mhz 176-lead lqfp st-176-1
rev. i | page 64 of 64 | august 2013 adsp-bf531 / adsp-bf532 / adsp-bf533 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03728-0-8/13(i)

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